A so-called current steering digital-to-analog converter has a plurality of cells which cooperate to realize high-speed digital-to-analog conversion. Each cell includes a current source and a differential switch which leads a current produced by the current source to a positive or negative output terminal. When a cell is arranged on a semiconductor integrated circuit chip, in general, a current source and a differential switch are arranged in different (i.e., separately-formed) regions to prevent degradation by digital noise of the accuracy of the current source. More specifically, current sources of all the cells are arranged in a form of matrix on a first region and differential switches of all the cells are arranged in a form of matrix on a second region which is different from the first region. Each of the current sources in the first region and each of the differential switches in the second region are electrically connected by metallic interconnect.
Usually, the number of cells included in a current steering digital-to-analog converter increases in accordance with the number of bits of the input digital signal. As the number of bits increases, the area of the first and second regions expands; as a result, the metallic interconnects connecting those regions need to be elongated.
Elongating metallic interconnects increases parasitic capacitance which accompanies the metallic interconnects. The greater the parasitic capacitance is, the greater the moving (i.e., charging and discharging) charge at the parasitic capacitor which is caused by on-off operation of the differential switch becomes. Thus, elongated metallic interconnects cause a larger spike voltage (such phenomena is called glitch) and lead to degradation of output signal accuracy.